(1) Field of the Invention:
The present invention relates to a constant-voltage generating circuit and, more particularly, to a constant-voltage generating circuit which is used such as in an internal voltage dropping circuit (step-down circuit) in a MOS memory circuit.
(2) Description of the Related Art:
First, an explanation will be given on the circuit and the operation of an internal voltage dropping circuit provided with a prior art constant-voltage generating circuit. FIG. 1 is a circuit diagram of the prior art constant-voltage generating circuit and FIG. 2 is a chart showing voltage dependencies with respect to power supply voltages at internal nodes.
In FIG. 1, symbols Q.sub.P 1 through Q.sub.P 5 each denotes a P-channel MOS field effect transistor (hereinafter simply referred to as a "PMOS"); Q.sub.N 1 denotes an N-channel MOS field effect transistor (hereinafter referred to as an "NMOS"); N1, N2 each denotes an internal node; and V.sub.REF denotes a constant-voltage output node. It should be noted that the PMOSs Q.sub.P 2 and Q.sub.P 3 have a higher current capability than that of the PMOS Q.sub.P 1 and the NMOS Q.sub.N 1. In the following explanation, a power supply voltage is represented by V.sub.CC, and an absolute voltage of threshold voltage of a PMOS transistor is represented by V.sub.TP.
Here, an explanation will be made as to how the potentials at the internal nodes N1, N2 and further at the output node V.sub.REF are determined.
The NMOS Q.sub.N 1 is always in a conductive state (on-state) since the gate potential thereof is at the power supply voltage V.sub.CC. Therefore, the potential at the node N2 falls towards a ground potential. Accordingly, the gate potential of the PMOS Q.sub.P 2 falls so that the PMOS Q.sub.P 2 turns on and, thus, the potential at the node N1 also falls towards the ground potential. As a result, the PMOSs Q.sub.P 1 and Q.sub.P 3, the gate terminals of which are connected with the node N1, turn on.
When all of the PMOSs Q.sub.P 1 through Q.sub.P 3 and the NMOS Q.sub.N 1 become conductive states, the potential at the node N1 becomes closer to the ground potential and that at the node N2 becomes closer to the power supply voltage V.sub.CC because of the relations to the current capability of the respective transistors concerned. As a result, the PMOS Q.sub.P 2 turns off, and the potential at the node N1 rises up to (V.sub.CC -V.sub.TP) again and becomes stable there. On the other hand, since the potential at the node N1 is (V.sub.CC -V.sub.TP) and thus the PMOS Q.sub.P 3 is in a non-conductive state, that is, "off-state", the potential at the node N2 drops towards the ground potential. When this potential at the node N2 drops to the (V.sub.CC -2.times.V.sub.TP) or lower, the PMOS Q.sub.P 2 turns on again. Then, the potential at the node N1 falls again so that the PMOS Q.sub.P 3 turns on and the potential at the node N2 starts to rise. The potential at the node N2 becomes stable at (V.sub.CC -2.times.V.sub.TP) where the PMOS Q.sub.P 2 eventually turns on.
The potential (V.sub.CC -2.times.V.sub.TP) at the node N2 is applied to a gate terminal of the PMOS Q.sub.P 4. Then, since the voltage across the gate and source terminals of the PMOS Q.sub.P 4 is 2.times.V.sub.TP regardless of the V.sub.CC, the PMOS Q.sub.P 4 operates as a constant-current element. On the other hand, the PMOS Q.sub.P 5 is always in an conductive state, so that it substantially operates as a resistor (impedance) element, The voltage (hereinafter also referred to as "V.sub.REF ") appearing at the constant-voltage output node V.sub.REF becomes substantially constant, so that the circuit shown in FIG. 1 operates as a constant-voltage generating circuit as apparent from the graph shown in FIG. 2.
In recent years, a transistor used in a memory circuit has a tendency of being scaled down owing to the highly integrated memory circuit, and the size of its design rule has almost reached half micron. This gives rise to the problem of a lowering of reliability in the transistor due to hot carriers. This requires that a power supply voltage be reduced. On the other hand, in order to meet user's desires to continue to use the power supply voltage in the same value as is available now in view of its relationship with other products, it has been proposed to adopt an internal voltage dropping circuit which is about to be put in practical use. Such as internal voltage dropping circuit can be designed with the use of the constant-voltage generating circuit described above.
FIG. 3 shows an example of an internal voltage dropping circuit of the kind which is used for the above purpose. In FIG. 3, a reference numeral 1 denotes the constant-voltage generating circuit explained in connection with FIG. 1, symbols Q.sub.P 6 through Q.sub.P 8 each denotes a PMOS transistor; Q.sub.N 2 through Q.sub.N 4 each denotes an NMOS transistor; N3 denotes an internal node; and V.sub.INT denotes an output node for an internal dropped voltage.
The PMOSs Q.sub.P 6, Q.sub.P 7 and the NMOSs Q.sub.N 2 through Q.sub.N 4 constitute a current-mirror type amplifier which, using as a reference voltage the constant-voltage V.sub.REF generated at and forwarded from the constant-voltage generating circuit 1, serves to produce the same potential as the V.sub.REF at the internal dropped voltage output node V.sub.INT. More specifically, in such circuit construction, if the potential at the internal dropped voltage output node V.sub.INT falls from the constant-voltage V.sub.REF, the potential at the node N3 falls by the operation of the amplifier, so that the current supplying capability of the PMOS Q.sub.P 8 increases. Thus, the potential at the internal output node V.sub.INT rises again and returns to the desired constant-voltage. In contrast thereto, if the potential at the internal output node V.sub.INT rises from the desired constant-voltage V.sub.REF, the potential at the node N3 rises by the operation of the amplifier, so that the current supplying capability of the PMOS Q.sub.P 8 decreases. Thus, the potential at the internal output node V.sub.INT falls again and returns to the desired constant-voltage. Accordingly, the constant-voltage with a good response characteristic and sufficient current supplying capability can be provided at the internal dropped voltage output node V.sub.INT.
The voltage dropping circuit incorporating the conventional constant-voltage generating circuit described above has the following defects.
Generally, in operation, a large current flows through the MOS memory circuit for a short period of time, so that the power supply voltage fluctuates at a time unit of several nanoseconds. On the other hand, as mentioned above, the potentials at the nodes N1 and N2 in the constant-voltage generating circuit are (V.sub.CC -V.sub.TP) and (V.sub.CC -2.times.V.sub.TP), respectively, and thus the PMOSs Q.sub.P 1 through Q.sub.P 3 are in their conductive states which states are very close to the non-conductive states. In short, the node N1 is in a high impedance state. Therefore, if there occurs a fluctuation in the power supply voltage, the potential at the node N1 transiently shifts to the value which is determined by the ratio between the capacitance of the gates, diffusion layers and wirings connected to the node N1 with respect to the power supply source and the capacitance thereof with respect to the ground GND.
As already described above, since the PMOS Qp3 connected with the node N1 is designed to have a sufficient current supplying capability, the capacitance at the node N1 with respect to the power supply source V.sub.CC is larger than the capacitance at the same node N1 with respect to the ground GND. Therefore, when there occurs the above mentioned fluctuation in the power supply voltage, the potential at the node N1 shifts transiently and abruptly towards the power supply voltage V.sub.CC. As a consequence, the potential at the constant-voltage output node V.sub.REF also shifts towards the power supply voltage abruptly. This is a problem to be solved.